Grip-Pattern Recognition for Smart Guns

This paper describes the design, implementation and evaluation of a user-verification system for a smart gun, which is based on grip-pattern recognition. An existing pressure sensor consisting of an array of 44 x 44 piezoresistive elements has been used. An interface has been developed to acquire pressure images from the sensor. The values of the pixels in the pressure-pattern images are used as inputs for a verification algorithm, which is currently implemented in software on a computer. The verification algorithm is based on a likelihood-ratio classifier for Gaussian probability densities. First results indicate that it is possible to use grip-pattern recognition for biometric verification, when allowing a certain false-rejection and false-acceptance rate. However, more measurements are needed to give a more reliable indication of the systems performance

MOD/R : A knowledge assisted approach towards top-down only CMOS VLSI design

MOD/R models all views on the design space in relations. This is achieved by eliminating the package constraints, as are apparent in PCB oriented hardware description languages. Assisted by knowledge engineering it allows for a top-down, mostly hierarchical decomposition, virtually eliminating the need for bottom-up assembly

Ontwerptraject digitale IC's

De bekende Wet van Moore (genoemd naar Gordon Moore, een van de oprichters van Intel) stelt dat het aantal transistoren op een IC elke achttien maanden verdubbelt. De wet werd in 1965 geformuleerd en blijkt nog altijd bruikbaar te zijn. Lag het aantal transistoren van een complexe IC in het begin van de jaren zeventig rond de duizend; via een miljoen aan het begin van de jaren negentig groeide dit aantal naar circa een miljard in 2005. Een dergelijke mate van complexiteit kan alleen bereikt en beheerst worden: – Door gebruik te maken van geavanceerde synthesetechnieken. Deze stellen een ontwerper in staat vanuit een compacte beschrijving een grote schakeling te generen. Men gebruikt hierbij een hardware beschrijvingstaal om een schakeling op een bepaald abstractieniveau te beschrijven. Een of meer synthesegereedschappen zetten vervolgens zo’n beschrijving om in een lay-out die geschikt is voor fabricatie. – Door hergebruik van blokken van een ontwerp met een duidelijk gedefinieerde functionaliteit. In deze context wordt vaak de term IP-blok gebruikt, waarbij IP een afkorting is van Intellectual Property (intellectueel eigendom). De gedachte achter deze term is dat de ontwerper(s) van het blok tijd en moeite hebben geı¨nvesteerd in het ontwerp en dat het ontwerp daarom economische waarde vertegenwoordigt. Dit hoofdstuk gaat voornamelijk over het ontwerpen van digitale blokken op een IC door middel van standaardcelsynthese, de meest gangbare vorm van digitaal ontwerpen. Een standaardcel is een relatief kleine digitale schakeling (bijv. een NAND-poort, een full-adder of een flipflop) waarvan de lay-out en dus ook het transistorschema vastligt. Een standaardcel maakt deel uit van een standaardcelbibliotheek, een verzameling van elementaire schakelingen waaruit een synthesegereedschap kan kiezen bij de samenstelling van een ontwerp. Zo’n bibliotheek wordt meestal betrokken van een extern bedrijf (of van een gespecialiseerde afdeling van het eigen bedrijf)

Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms

This paper addresses the efficient implementation of highperformance signal-processing algorithms. In early stages of such designs many computation-intensive simulations may be necessary. This calls for hardware description formalisms targeted for efficient simulation (such as the programming language C). In current practice, other formalisms (such as VHDL) will often be used to map the design on hardware by means of logic synthesis. A manual, error-prone, translation of a description is then necessary. The line of thought of this paper is that the gap between simulation and synthesis should not be bridged by stretching the use of existing formalisms (e.g. defining a synthesizable subset of C), but by a language dedicated to an application domain. This resulted in Arx, which is meant for signal-processing hardware at the register-transfer level, either using floating-point or fixed-point data. Code generators with knowledge of the application domain then generate efficient simulation models and synthesizable VHDL. Several designers have already completed complex signal-processing designs using Arx in a short time, proving in practice that Arx is easy to learn. Benchmarks presented in this paper show that the generated simulation code is significantly faster than SystemC

Extraction of Singular Points from Directional Fields of Fingerprints.

Biometric identification is an emerging subject in applications like high-security wireless access and secure transactions across computer networks. Fingerprints are easy to use and provide relatively good performance. Furthermore, fingerprint sensors are cheap and can be integrated easily in wireless hardware. In this paper, methods are presented for the estimation of a high resolution directional field from fingerprints. It is shown how, from the directional field, very accurate detection of the singular points and the orientations of those points can be obtained. These estimates can for instance be used for accurate registration (alignment) of two fingerprints in a fingerprint verification system

Overlapped scheduling techniques for high-level synthesis and multiprocessor realizations of DSP algorithms

Algorithms that contain computations that can be executed simultaneously, offer possibilities of exploiting the parallelism present by implementing them on appro priate hardware, such as a multiprocessor system or an application-specific inte grated circuit (ASIC). Many digital signal processing (DSP) algorithms contain in ternal parallelism and are besides meant to be repeated infinitely (or a large number of times). These algorithms, therefore, not only have intra-iteration parallelism (between operations belonging to the same iteration) but inter-iteration parallelism (between operations belonging to different iterations) as well [Par9 1]

Multicore soc for on-board payload signal processing

This paper introduces a new generic platform for onboard payload signal processing. The system is built up around an NoC with a bridge to an AMBA system which supports easy integration with existing AMBA based platforms. With the use of a pthreads interface the platform allows for simple programming and easy extension. For prototyping purposes, an implementation has been made on an FPGA together with a range of I/O options to assess its capabilities. SpaceWire and other interfaces support the extension of the demonstrator platform across multiple boards and allow to connect it to onboard networks and systems. This paper shows that novel and established chip architectures can be integrated in a way that combines their benefits, and represents a promising candidate architecture for future on-board processing platforms

Balanced cut approximation in random geometric graphs

A random geometric graph is obtained by spreading n points uniformly at random in a unit square, and by associating a vertex to each point and an edge to each pair of points at Euclidian distance at most r. Such graphs are extensively used to model wireless ad-hoc networks, and in particular sensor networks. It is well known that, over a critical value of r, the graph is connected with high probability. In this paper we study the robustness of the connectivity of random geometric graphs in the supercritical phase, under deletion of edges. In particular, we show that, for a sufficiently large r, any cut which separates two components of Θ(n) vertices each contains Ω(n2r3) edges with high probability. We also present a simple algorithm that, again with high probability, computes one such cut of size O(n2r3). From these two results we derive a constant expected approximation algorithm for the β-balanced cut problem on random geometric graphs: find an edge cut of minimum size whose two sides contain at least β n vertices each. © 2006 Springer-Verlag Berlin/Heidelberg